Many applications for video coding currently exist, including applications for transmission and storage of video data. Many video coding standards have also been developed and others are currently in development. Recent developments in video coding standardisation have led to the formation of a group called the “Joint Collaborative Team on Video Coding” (JCT-VC). The Joint Collaborative Team on Video Coding (JCT-VC) includes members of the Video Coding Experts Group (VCEG) of the Telecommunication Standardisation Sector (ITU-T) of the International Telecommunication Union (ITU) and members of the Moving Picture Experts Group (MPEG) of the International Organisations for Standardisation/International Electrotechnical Commission (ISO/IEC).
The Joint Collaborative Team on Video Coding (JCT-VC) has the goal of producing a new video coding standard to significantly outperform a presently existing video coding standard, known as “H.264/MPEG-4 AVC”. The H.264/MPEG-4 AVC standard is itself a large improvement on previous video coding standards, such as MPEG-4 and ITU-T H.263. The new video coding standard under development has been named “high efficiency video coding (HEVC)”. The JCT-VC is also considering implementation challenges arising from technology proposed for high efficiency video coding (HEVC) that create difficulties when scaling implementations of the standard to operate at high resolutions or high frame rates.
One area of the H.264/MPEG-4 AVC video coding standard that presents difficulties for achieving high compression efficiency is the coding of residual coefficients used to represent video data. Video data is formed by a sequence of frames, with each frame having a two-dimensional array of samples. Typically, frames include one luminance and two chrominance channels. A video encoder compresses the video data into a bitstream by converting the video data into a sequence of syntax elements.
In high efficiency video coding (HEVC) and in H.264/MPEG-4 AVC, a prediction for a current frame is derived, based on reference sample data either from other frames, or from other regions within the current frame that have been previously decoded. The difference between the prediction and the desired sample data is known as the residual. A frequency domain representation of the residual is a two-dimensional array of residual coefficients. By convention, the upper-left corner of the two-dimensional array contains residual coefficients representing low-frequency information.
In typical video data, the majority of the changes in sample values are gradual, resulting in a predominance of low-frequency information within the residual. This manifests as larger magnitudes for residual coefficients located in the upper-left corner of the two-dimensional array.
A context adaptive binary arithmetic coding (CABAC) scheme is defined within the high efficiency video coding (HEVC) standard under development. In the high efficiency video coding (HEVC) standard under development, when context adaptive binary arithmetic coding (CABAC) is enabled, each syntax element is expressed as a sequence of bins, where the bins are selected from a set of available bins. Creating such a sequence of bins from a syntax element is known as “binarising” the syntax element.
When implementing context adaptive binary arithmetic coding (CABAC), the binary arithmetic decoding algorithm has a feedback dependency loop. The feedback dependency loop is between a context selector, for determining which context from the context model to use for a current bin, a context modeller, for updating context information of each bin, and an arithmetic coder. The context selector uses values of previously decoded bins to determine the context for the current bin. In an encoder, the process of context selection is referred to as “binarisation”. In a decoder, the process of context selection is referred to as “inverse binarisation”. The length of the feedback dependency loop limits bin throughput achievable in hardware implementations of binary arithmetic coding (BAC) for a given clock frequency. The limitation in bin throughput is relevant when an implementation is required to provide higher bin throughput.
The property of low-frequency information being predominant in the upper-left corner of the two-dimensional array of residual coefficients may be exploited by the chosen binarisation scheme to minimise the size of the residual coefficients in the bitstream.
A provided scan pattern enables scanning the two-dimensional array of residual coefficients into a one-dimensional array. In the two-dimensional array of residual coefficients, those having a nonzero value are referred to as significant residual coefficients and those having zero value are referred to as non-significant residual coefficients. A two-dimensional array representing only the “significant” status of each residual coefficient is referred to as a significance map. By scanning the significance map using the provided scan pattern, the location of the last significant residual coefficient in the two-dimensional significance map may be determined Scan patterns may be horizontal, vertical, diagonal or zig-zag.
The location of the last significant residual coefficient is binarised into the bitstream, requiring two syntax elements to represent the X and Y component of the location. As the residual coefficients located after the last significant residual coefficient are known to be non-significant there is no need to store them in the bitstream. The significant status of residual coefficients located prior to the last significant residual coefficient is not known and therefore this portion of the significance map must be stored in the bitstream.
There are two disadvantages to this scheme. Firstly, in order to encode the location of the last significant residual coefficient in the two-dimensional significance map, two indices must be stored in the bitstream. Secondly, as the last significant residual coefficient could be located in any position within the two-dimensional significance map, implementations which encode multiple significant residual coefficient flags per clock cycle must have additional multiplexing logic in order to support encoding a variable number of significant residual coefficients per clock cycle. This additional multiplexing logic increases the logic path delay in the circuit, reducing the maximum achievable clock speed of a high efficiency video coding (HEVC) hardware implementation.
Higher bin throughput is required to support video formats offering higher frame rates and higher resolutions, such as ultra-high definition television (UHDTV), super hi-vision (SHV) or wide quad high definition (WQHD).